In order to reduce overall integrated circuit (i.e., chip) test costs, many modern chips are fabricated with built-in self-test (BIST) circuitry. Such circuitry is considered “built-in” as it is included on the chip itself. This can allow for internally generated test patterns to be applied to a portion of the chip.
The manufacture of integrated circuit devices can be conceptualized as including a “front-end” and a “back-end.” A manufacturing front end may include the fabrication of devices on a wafer. A back-end may include slicing wafers into dice, packaging the dice, and testing the resulting packages. With the increasing speed and/or complexity of integrated circuit devices, testing can become an important step in a manufacturing process.
Back-end testing may include a range of possible tests. For example, at one end of the spectrum, such tests can be basic structural tests checking for opens and shorts in the logic circuits of a programmable logic device. At the other end of the spectrum, such tests can check performance features of the chip, such as operational speed, etc. Such tests can allow non-failing devices to be categorized (binned) according their operating characteristics (e.g., speed).
In some arrangements, a tester can be loaded with a test program that exercises various functions of an integrated circuit device. Such an approach can be time consuming as a tester must apply various input signals and wait for the resulting test result signals. In addition, between different devices and/or different tests, test program data may have to be loaded into the tester.
One way to address the complexity, cost and delay in testing integrated circuit devices has been to include self-test circuits on the device itself. Such approaches have been referred to as “built-in self-test” (BIST). BIST capabilities can reduce test times, as the on-board BIST circuits can apply test signals, typically faster than a tester. Further, instead of having a tester sequence through various functions and accumulate results, a tester may only have to read a pass or fail indication. Consequently, simpler, less expensive testers can be used.
To better understand various aspects of the invention, a chip with a conventional BIST circuit will now be described.
FIG. 5 shows a conventional chip arrangement having a BIST capability. A conventional chip 500 can include a BIST block 502 separated from a main chip portion 504. BIST block 502 can test a main chip portion 504. A main chip portion 504 may be a memory array, as but one example. A BIST block 502 can interface directly with a main chip portion 504 and generate an input test pattern for application to the main chip portion 504.
A conventional chip 500 can include bond pads 506-0 to 506-2. Bond pads (506-0 to 506-2) include a clock bond pad 506-0, an address bond pad 506-1, and a control bond pad 506-2. Bond pads (506-0 to 506-1) can also directly interface with the main chip portion 504. However, bond pads (506-0 to 506-1) do not interface with BIST block 502.
As is well understood, bond pads (506-0 to 506-1) can connect to off-chip connections, such as to other chips and/or circuit boards and/or test systems. Thus, a tester, or other chips in an application, can supply signals through such bond pads (506-0 to 506-1) to test, characterize and/or to otherwise access the chip 500.
Most conventional BIST configurations can be used to check various logic states in a main chip portion 504, such as a memory array. However, conventional BIST configurations are not well suited for characterizing timing parameters. Timing parameters can typically reflect signal propagation for an entire timing path of a chip, including input structures such as bond pads, and the like. As a result, conventional BIST configurations provide no emulation of the actual path of signals propagating from the tester through chip bond pads.
Also, many conventional BIST test patterns typically only work for certain critical paths and the overall test coverage relative to a full set of main chip functions and/or states can be low. Because test patterns are usually directly applied to the main chip portion 504, a conventional BIST block 502 is not configured to test such timing parameters as setup time (Ts), hold time (Th), clock-to-output time (Tco), and clock cycle time (Tcyc).
As is well known, a setup time (Ts) can be a time leading up to a clock event during which input data must remain stable in order to guarantee the data values are captured. A hold time (Th) can be the time following a clock event during which input data must remain stable in order to guarantee the data values are captured. A clock-to-output time (Tco) can be the time between a clock event and a particular output signal. A clock cycle time (Tcyc) can be a minimum cycle time at which a chip 500 can operate. Effective characterization of these and other types of timing parameters can be very important for many chips. As but one example, such timing parameters can be important for synchronous static random access memories (SRAMs).
Accordingly, characterization of critical timing parameters has conventionally been accomplished by dropping tester probes onto bond pads and applying sets of test signals (i.e., vectors) to a chip. As noted above, this can be time consuming, complex, and expensive. Such testing of timing critical parameters is typically accomplished by a high speed “class” tester that can be very costly to purchase and or operate.
In light of the above, it would be desirable to arrive at some way of improving the speed and/or ease at which timing parameters are tested for an integrated circuit device.